According to the studies by the inventors of the present invention, the following technologies are known in the field of a semiconductor device such as a SRAM (Static Random Access Memory).
Most of current SRAMs incorporate a voltage step-down circuit, and internal circuits of the SRAM are operated by the internal voltage obtained by stepping-down the external voltage in this voltage step-down circuit. This internal voltage is an important voltage because it influences the stability of the operation of the internal circuits. Therefore, in the sorting process before the shipment of the packaged products, the evaluation of the internal voltage is performed while changing the internal properties through the pseudo trimming by the JTAG function (IEEE standard 1149.1 proposed by Joint Test Action Group) so as to screen the samples with small margin (Japanese Patent Application Laid-Open Publication No. 2003-242799 (Patent document 1)).
The invention described in patent document 1 enables the trimming after sealing the semiconductor chip into a package. More specifically, control means for switching the trimming mode and the evaluation mode for the internal circuits is provided, this control means includes a control unit which can perform the mode switching control of the trimming mode and the evaluation mode through the method of JTAG, and the control unit includes a command decoding unit for decoding the inputted command, a shift scan register group for performing the boundary scan based on the decoding results in the command decoding unit, and an operation control unit for controlling the operation of the command decoding unit and the shift register. In this structure, the trimming after sealing the semiconductor chip into a package can be achieved.